The present invention relates to a resin-molded type of semiconductor device package and more particularly to an improvement in the construction of a leaded chip carrier package.
In a resin-molded type of semiconductor device package, a chip, which is a circuit element, is mounted on the chip-mounting portion of a lead frame. The lead frame is formed as a unitary structure, the chip is connected to internal leads through wires, and a resin is molded around the chip, the wires, and the internal leads. A package of this type can be manufactured at a lower cost than ceramic-type packages.
In recent years, a variety of types of chip carriers have been proposed to meet the demand for the construction of smaller-sized packages. A ceramic-type chip carrier having no external leads is called a leadless chip carrier. A resin-molded type of chip carrier having short external leads is called a leaded chip carrier which has a cost advantage over the ceramic-type chip carrier. Both ceramic-type chip carriers and resin-molded chip carriers are constructed so that they are small in size, and both are mounted on a printed circuit board by means of a simple soldering operation. It is unnecessary to insert the external leads into the holes of the printed board, as is necessary in the case of conventional dual in-line package.
In the known resin molded leaded chip carriers, the leads, which are flat, are soldered on the conductor patterns of a printed circuit board having a flat plane. The following drawbacks are created:
1. Whether soldering is complete cannot be determined by viewing the exterior of the package. PA0 2. When there is a projection on the printed circuit board the leads of the chip carrier do not completely contact the conductor patterns of the printed circuit board, with the result that soldering of the chip carrier to the printed circuit board cannot be effected. PA0 3. The mechanical strength of the connection between the leads and the conductor patterns by the solder is weak. PA0 4. The leads cannot completely absorb the difference in the heat expansion coefficient between the printed board and the chip carrier, with the result that undesirable stresses are created on the leads. PA0 1. The manufacturing process, particularly the lead bending operation is not easy. PA0 2. The flux used in the soldering operation remains in the hollow portions of the main surface. PA0 3. The soldering state cannot be visually examined from the exterior of the package because of the projecting portions. PA0 4. When the number of leads is increased in accordance with the development of a high density integratedcircuit device, the neighboring external leads are often short-circuited if they are deformed, and the standoff distance, a necessary distance between the mother board and the main surface of the package when the chip carrier is mounted, is no longer maintained.
A chip carrier assembly having a standoff distance and having the objective of eliminating the above-mentioned drawbacks was disclosed in IEEE Transactions On Components, Hybrids, And Manufacturing Technology, Vol. CHMT-3, No. 4, December 1980, "Development of a 68-Pin Multiple In-Line Package" by William L. Brodsky et al. However, the chip carrier assembly disclosed by William L. Brodsky et al has the following drawbacks: